Technical Field
The present invention relates generally to semiconductor devices, and more specifically, to the selective deposition and nitridization of a bottom electrode metal for at least magnetic random access memory (MRAM) applications.
Description of the Related Art
Integrated circuits are typically fabricated with multiple levels of patterned metallization lines, electrically separated from one another by interlayer dielectrics containing vias at selected locations to provide electrical connections between levels of the patterned metallization lines. As these integrated circuits are scaled to smaller dimensions in a continual effort to provide increased density and performance (e.g., by increasing device speed and providing greater circuit functionality within a given area chip), the interconnect linewidth dimension becomes increasingly narrow, which in turn renders them more susceptible to effects such as electromigration.